Sunday, 15 April 2012

Backend PnR Flow

The design implementation flow or the physical design flow is broadly classified into the following five steps:
     1. Design initialization
     2. Pre-CTS flow
     3. Post-CTS flow
     4. Postroute flow
     5. Signoff
To sail through all these steps smoothly a physical design Engineer must be an expert in TCL/perl scripting without which he is no less to a soldier without a gun. The saint walks you through the complete flow thoroughly.

1. Design initialization

This is first and very important step for implementing a netlist to GDSII. This include
    I. Environment Setup
    II. Design Setup
    III. Floorplanning and Powerplanning

I. Environment Setup:

This involves creation of all the directories in your run environment which includes the directories to save your projects, back annotation directory, logs etc. This will greatly help in segregating your work in a orderly fashion

II. Design Setup:

This is the stage where you read in your input netlist (synthesis netlist), SDC constraints, the .lib and .lef files, UPF and a scandef at a minimum to setup your design. After reading these input files you link the design by creating the scenario files based on different PVT conditions. Linking is nothing but associating leaf level reference cells in netlist with cells from library. You should ensure that you resolve all the linking errors which include missing .lib's, .lef's before proceeding to further step. After linking you uniquify your design.

III. Floorplanning and Powerplanning:

Before looking at guidelines for design planning, it is worth reviewing the reasons for taking time to create a good floorplan and power layout. Create a floorplan to meet your timing and area constraints. Floorplanning include following steps
  • Defining core and die area
  • Placing pins or IO pads
  • Placing macros
The core and die area should be defined in such a way that the utilization of the area is good enough to accomodate all the standard cells and also additional cells that get added during the optimization and the clock tree building. The best utilization to start of with PnR is somewhere in between 65%-70%. The pins or IO pads are placed depending on whether it is a block level or top-level modules. The placement of pins, macros or the hard IP's are done based on the data-flow diagram and are made fixed. This helps in making the timing critical paths short, by preventing routing congestion that can lead to longer paths. This also helps in accomodating the signal integrity issues due to noise sensitivity of the Analog IP's.
Besides floorplan constraints, we see power issues that are more challenging in lower technologies due to additional metal layers and thinner wires. Better power planning helps in overcoming the problems like IR drop and electromigration. Power planning prevents problems by making sure that each part of power mesh has sufficient current-carrying capacity. This power mesh should be done taking into account the DRC rules.

2. Pre-CTS flow

The pre-CTS flow comprises of the standard cell placement and placement timing optimization. Better timing, power and area are the design goals in this particular phase. placement optimization engine of the tool meets these goals by eliminating the placement congestion and ensuring that design is routable based on a trial route analysis. The timing numbers in this stage are based on a ideal clock tree. In a nutshell the tool will do placement of the cells (which could be SI and power aware in lower technologies), high-fanout buffering, logic restructuring to meet timing, cell sizing, buffering, cloning, Vtswapping for leakage optimization, area reduction.
Scanchain reordering is an important step in the pre-CTS flow. Scan chains can be reordered based on global placement to reduce the wirelength and hence congestion. This comes as an input from DFT in the form of a scandef. Here all the flops are connected in the form of a chain where data can be shifted in or out of these flops.
After doing the initial placement, scan chain reordering and optimization it will do legalize placement where it will find the nearest legal location and place them.

3. Post-CTS flow

The post-CTS flow includes clock tree synthesis and timing optimization of the design. Till the pre-CTS flow all the clock nets were treated as ideal. This would mean that you would see zero clock skews and zero clock latency. So, after pre-CTS flow we build CTS which mean building a buffer tree on high fanout clock nets and optimizing the clock paths. This is achieved by specifying targets to the CTS tool. These targets include global clock skew, maximum transition limit, minimum insertion delay, maximum capacitance and maximum fanout limit.

While building the clock tree there is one more important factor called OCV (On Chip Variation) which plays a major role. In order to account for the proper design operation across variation space, timing verification has to be performed on all relevant combination of processes and environmental parameters. This need for accurately capturing process variations on design side has led to the introduction of OCV which is nothing but an additional pessimism for the timing requirements.
This is followed by the post-CTS timing optimization where in you optimize the datapath based on the additional delays you see because of the clock skew. Hold violations are likely to show up which could be fixed by the addition of a buffer or downsizing a cell.

4. Postroute flow

Till now the tool would have placed the instances based on the trial route information which is not accurate. In the postroute flow the toold does a global detail route followed by setup/hold timing optimization based on the extracted parasitic values which constitute to the actual delays and post-SI setup and hold fixing
Routing in layman words is nothing but establishing a physical connection for the corresponding logical connection using different metal layers and vias. Routing is done by the tool based on a set of rules called as DRC rules. Some of the DRC rules are given below:
  • Definition of different metal layers and their routing direction, minimum width and spacing constraints.
  • Min-area, min-edge, notch rules etc.
  • Defining vias, their size and the spacing requirements.
In this phase first the tool divides the whole die into small buckets and estimate the congestion in the buckets based on the number of tracks it can accomodate. This is the global routing step.
After this is done the tool assigns actual track and the metal layer to each net and then does the detail routing. In this step the tool tries to fix the open nets and also DRC violations if any.
Once the routing is done the tool does RC extraction and get the actual delay numbers of the nets and also the cell delays. Based on this it updates the timing. This is followed by the routing optimization step wherein the violations calculated based on the actual RC delay values are fixed.
SI (Signal Integrity) is an important parameter which plays a significant role in detail routing. Signal integrity ensures the electrical performance of the chip. This relates to the core power delivery, interconnect crosstalk, noise etc. Since the detail routing is SI aware we get to see the coupled noise (crosstalk). This is caused if two signal lines are close to each other in a way that the electric and magnetic fields generated due to one line couples with another line causing coupled noise on other line. This can be taken care by following some custom-width rules, keeping coupling length smaller etc.

5. Signoff

The signoff phase consists of 3 steps
    I. Metalfill
    II. Timing Analysis
    III. Physical Verification

I. Metalfill

This is the process of adding metal wire shapes to the design that are required to meet foundry metal density rules. But this can impact the capacitance of the surrounding wires and in turn affect the timing and signal integrity.

II. Timing Analysis

The impacts of metalfill on timing are analyzed and timing is closed in all respects i.e setup as well as hold. All the maximum transition violations and maximum capacitance violations are also fixed in the signoff STA (Static Timing Analysis) tool.

III. Physical Verification

GDSII is dumped from the database and it is taken through DRC and LVS in the signoff tool which is generally Mentor Graphics's calibre tool.
Apart from these checks other checks that include in the flow before shipping the GDSII are
  • Static/dynamic IR Drop analysis
  • Power/Signal EM checks
  • Gridchecks
Placement of the macros and IO pin placement are the key things which help in achieving your goal of delivering a timing clean database and a good quality product.




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